This invention relates generally to transistortransistor-logic (TTL) circuitry, and more particularly, it relates to a TTL buffer circuit which includes an active turn-off means so as to provide faster output transitions without using excess power consumption.
Typically, TTL buffer circuits respond to an input signal either by coupling an output terminal to a supply voltage via an active pull-up device when the input signal is in a first logic state or by coupling the output terminal to a ground potential via a pull-down device when the input signal is in a second logic state. A conventional TTL buffer circuit is illustrated in FIG. 1 and has been labeled as "Prior Art."
In FIG. 1, the TTL buffer circuit 10 includes an input terminal 12 and an output terminal 14. A bipolar PNP transistor Q400 has its base connected to the input terminal 12 and is responsive to an input signal OEB which may assume a first or second logic level or state, its emitter coupled to a supply potential or voltage VCC via a resistor R400, and its collector connected to a ground potential. The supply potential VCC is typically +5.0 volts. A Schottky bipolar NPN transistor Q401 has its base connected to the emitter of the transistor Q400, its collector coupled to the supply potential VCC via a resistor R401, and its emitter coupled to the ground potential via a resistor R402. The emitter of the transistor Q401 is also connected to the anode of a Schottky diode D400 and to the base of a phase splitter transistor Q408. The cathode of the Schottky diode D400 is connected to the input terminal 12.
The collector of the phase splitter transistor Q408 is connected to one end of a resistor R415 and to the base of a bipolar pull-up NPN transistor Q411. The other end of the resistor R415 is connected to the supply potential VCC. The emitter of the phase splitter transistor Q408 is connected to one end of a resistor R412 and to the base of a bipolar pull-down NPN transistor Q413. The other end of the resistor R412 is connected to the ground potential. The pull-up transistor Q411 has its collector coupled to the supply potential VCC via a resistor R414 and its emitter connected to the collector and base terminals of a diode-connected transistor Q412. The emitter of the transistor Q412 is connected to the collector of the pull-down transistor Q413, one end of a resistor R416, and the output terminal 14. The other end of the resistor R416 is connected to the supply potential VCC. The pull-down transistor Q413 has its emitter connected to the ground potential.
When the input signal OEB having a low logic level is applied to the input terminal 12, a low logic level will also appear at the base of the phase splitter transistor Q408 and thus no current will be conducted through its collector to emitter thereby turning off the pull-down transistor Q413. As a result, drive current will be supplied to the base of the pull-up transistor Q411 to cause its emitter to source current through the output terminal 14. Therefore, the output signal OE at the output terminal 14 will be at a high logic level. It will be noted that the resistor R412 provides only a passive turn-off since only a discharge current ##EQU1## is available for turning off the pull-down transistor Q413.
When the input signal OEB having a high logic level is applied to the input terminal 12, a high logic level will be translated to the base of the phase splitter transistor Q408 which renders the transistor Q408 to be conductive and sinks current away from the base of the pull-up transistor Q411. As a result, current from the supply potential VCC will no longer be sourced to the output terminal 14. At the same time, the pull-down transistor Q413 will be rendered conductive through its collector to emitter to ground due to the drive current supplied to its base. Therefore, the output signal OE at the output terminal 14 will be at a low logic level.
It would desirable to increase the speed of the low-to-high and high-to-low output transistions at the output terminal when the appropriate input signal is received at the input terminal without causing excess power dissipation. This is achieved by the present invention through the provision of an active turn-off means.